As part of our Digital Electronics (CS56) course at Dartmouth, my partner, Jake Epstein, and I decided to build an RSA security hardware module using an FPGA. We implemented both RSA key generation and encryption/decryption functionalities from scratch on the Xilinx Basys3 Board using the VHDL hardware description language. This research project involved extensive research, approx. 4000 lines of code development in VHDL, and hands-on hardware testing.

As a part of the project, we generated a ~60 page research report, complete with simulation figures from Xilinx Vivado (a software used to simulate FPGA codes before they are placed on harware), and logic diagrams describing logic flow in our RSA module. Click a link above to learn more about VHDL and FPGAs, or visit the github page to read our research report or view our code.